module TAGV_RAM(
  input [7:0] addra,
  input clka,
  input [20:0] dina,
  output [20:0] douta,
  input wea
);

  reg [7:0] addra_r;
  reg [20:0] mem [255:0];
  
  always@(posedge clka) begin
    if (wea) begin
      mem[addra] <= dina;
    end
    
    if (!wea) begin
      addra_r <= addra;
    end
  end
  
  assign douta = mem[addra_r];

endmodule
